Benefit from an immediate design-free, dynamic performance gain
- The new EV12AQ600/605-ADX4 device options now feature an integrated ADX4 license key enabling enhanced dynamics when operating at up to a peak of 6.4 GS/s (single channel mode).
- ADX4 – a post-processing algorithm compatible with Xilinx Kintex® Ultrascale™ FPGAs delivers up to 10 dBFS of SFDR dynamic spurs reduction and close to 1 effective bit extra resolution in broadband applications.
- Time-interleaving, whilst providing a conceptually easy to comprehend sample rate boost, is challenging to achieve at extended resolutions and wide bandwidths.
Gain immediate, design-free access to a dynamic boost for the EV12AQ600/5
GRENOBLE, FRANCE – Media OutReach – 17 June 2022 – Teledyne e2v today announces the immediate availability of EV12AQ600/5 models featuring an integrated license key providing direct access to the novel ADX4 post-processing algorithm developed at SP Devices within the Teledyne group of companies. The ADX4 spur reduction IP dynamically attenuates spurious frequency components resulting from gain, offset and phase mismatches between the four ADC cores. Time-interleaving is a trusted architectural approach to boost ADC sampling rates. However, avoiding resulting spectral artifacts with calibration is especially challenging beyond 10-bit resolutions and in broadband applications.
